Array of values loaded through UART in VHDL -

i working on project in vhdl wich includes mutliplying matrices. able load data pc arrays on fpga using uart. making first bigger steps in vhdl , not sure if taking right attitude.

i wanted declare array of integer signals, , implement uart receive data form pc , load signals. however, can't use for-loop that, synthesised load data parallelly (which impossible, because values comming pc 1 after another, using serial port.) , because matrices may various sizes, in order assign signals 1 one need write lots of specific code (and appears bad practice me.)

is idea use array of signals , load data signals through uart realizable? , if approach entirely wrong, how achieve that?

what want doable need design kind of hardware monitor act intermediate between uart , storage (your array of integer signals). hardware monitor interpret commands coming uart , perform read/write operations in storage. have 1 interface storage , uart. have define kind of protocol syntax commands , of sequences of operations each command.

example: monitor waits commands coming uart. first received character indicates whether read (0) or write (1). 4 next characters target address, least significant byte first. if command read, monitor reads data @ specified address in storage , sends uart, 1 byte @ time, least significant byte first. if command write, address followed data write in storage @ specified address, least significant byte first, , monitor waits until data received , writes in storage.

optionally, monitor send exit status byte @ end of each command indicate potential errors (protocol errors, unmapped addresses, write attempts in read-only regions...)

of course, depending on characteristics of application, define different protocol, simpler or more complex, principle same.

all implemented in software , runs on cpu has uart peripheral , storage in memory space. if not have cpu...

warning: quite complex. uart quite complex. not sure should start if vhdl beginner.